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Michele Ancis
Austria
11 Posts |
 Posted - Dec 06 2021 : 14:53:37
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Hi,
I am trying to reproduce a stack used in another simulator, to double-check some of its results. Due to the possibility to draw certain types of structures (I think, I'm not the provider of this stack definition, only its user), the dielectric stack is organized with "dummy" layers, i.e. interfaces with certain heights but between materials with same dielectric constant.
When implementing this in FasterCap and running a simulation, I get this warning:
Warning: dummy dielectric-dielectric interface found in the input file, skipping
Question: is it safe to assume FasterCap is "doing the right thing" and neglecting that interface?
Or can this be a source of trouble for the simulator?
The metal shapes are defined "as if" this dummy interface wasn't there, i.e. a rectangular conductor is defined by two files connected and immersed in two different dielectric media (because there is a "real" dielectric interface between the sides and the top of the conductor, it's a classic planar IC process stack).
The U-shaped bottom metal is actually crossing one of these "dummy interfaces" but since the epsilonR is equal between the two, I did not split the geometry.
The simulation gives rise to a not diagonally dominant cap matrix, but this can be dependent on the nature of the problem.
Thanks in advance for your inputs,
Michele |
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Michele Ancis
Austria
11 Posts |
Posted - Dec 06 2021 : 17:32:01
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As a follow/up from my previous post, I have now tried to fuse together the "dummy dielectrics" as they actually do not play any role in my simulations (they mark some important heights in the structure but are otherwise of no value).
The numerical results are very close together, so I think it is safe to say that the "disturbance" introduced by them is minimal.
I would still be interested in knowing your opinion.
Regards,
Michele |
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Enrico
545 Posts |
Posted - Dec 06 2021 : 20:03:38
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Hi Michele,
you don't need to worry.
FasterCap warns you about this condition as this might flag an unwanted definition in the input file (i.e. a user's mistake); but otherwise ignores the dummy interface, as in fact there is no actual interface. This is the meaning of the warning message.
Best Regards,
Enrico
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KSergP
Russia
5 Posts |
Posted - Feb 01 2022 : 04:17:37
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Hi.
Sorry if I wrote in the wrong place, but I did not want to produce extra branches in the forum
Tell me where you can read how the calculation of the capacitive matrix is implemented in the 2-D case. Because, in paper
K. Nabors and J. White. FastCap: A Multipole Accelerated 3-D Capacitance Extraction Program // IEEE Trans. on Computer Aided Design of Integrated Cirucits and Systems, 10(11):1447–1459, November 1991
described how to compute only in 3-D.
(As I understand it, 2-D uses a different Green's function and therefore integrals are easier to calculate.)
I looked through the Literature section on your site, but did not find a description.
Thanks in advance
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Enrico
545 Posts |
Posted - Feb 01 2022 : 10:05:46
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Hi KSergP,
actually I would have preferred if you had created a new thread in the Forum, also because it makes easier for other users to find the same information; not a big issue, but next time please go ahead and open a new stream of discussion.
Anyway, I believe your point has already been addressed in the thread ht*ps://w*w.fastfieldsolvers.com/forum/topic.asp?TOPIC_ID=1524 (just replace ht*ps and w*w with the proper letters - obfuscating with * is only an anti-spam measure of the forum)
If you still have questions, please feel free to ask.
Best,
Enrico
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FasterCap 2D - Dummy dielectric-dielectric interf
