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omar
8 Posts |
 Posted - May 03 2017 : 18:50:43
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Hello all,
I'm trying to model coupling capacitance in IC interconnect as the following:
conductorA==dielectric_2==conductorB==dielectric_2==conductorC==dielectric_2==conductorD
The four conductors have same rectangular dimensions: length= 5um, width= 70nm, thickness= 140nm
The 4 conductors are separated apart by 70nm which is occupied by dielectric_2. I want to model "dielectric_2" to have the same geometrical structure as the four conductors. So I want these wires to create a sandwitch structure. The surrounding dielectric of this whole structure should be dielectric_1 (not air).
Here's what I've done so far (since I'm working with nanometers, so I multiplied all lengths with 1e9 and divided dielectric value with 1e9):
This is the file containing one conductor description: ( I should use it for all conductors + dielectric_2)
C myWire 0.0 0.0 0.0 5000 0.0 0.0 5000 70 0.0 0.0 70 0.0 +
C myWire 0.0 0.0 140 5000 0.0 140 5000 70 140 0.0 70 140 +
C myWire 0.0 0.0 0.0 5000 0.0 0.0 5000 0.0 140 0.0 0.0 140 +
C myWire 0.0 70 0.0 5000 70 0.0 5000 70 140 0.0 70 140 +
C myWire 0.0 0.0 0.0 0.0 0.0 140 0.0 70 0.0 0.0 70 140 +
C myWire 5000 0.0 0.0 5000 0.0 140 5000 70 0.0 5000 70 140
but I'm stuck in how to represent this design, so can anybody help me writing the main .lst file ?
Omar Alaa |
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omar
8 Posts |
Posted - May 03 2017 : 19:08:43
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I'm sorry the code attached should be like this:
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Q myWire 0.0 0.0 0.0 5000 0.0 0.0 5000 70 0.0 0.0 70 0.0
Q myWire 0.0 0.0 140 5000 0.0 140 5000 70 140 0.0 70 140
Q myWire 0.0 0.0 0.0 5000 0.0 0.0 5000 0.0 140 0.0 0.0 140
Q myWire 0.0 70 0.0 5000 70 0.0 5000 70 140 0.0 70 140
Q myWire 0.0 0.0 0.0 0.0 0.0 140 0.0 70 0.0 0.0 70 140
Q myWire 5000 0.0 0.0 5000 0.0 140 5000 70 0.0 5000 70 140
Omar Alaa |
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omar
8 Posts |
Posted - May 04 2017 : 15:37:11
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any help please ?
Omar Alaa |
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Enrico
545 Posts |
Posted - May 04 2017 : 18:13:06
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Is dielectric_2 having a width of exactly 70 nm, just like the conductors?
In this case, you need to split the faces of the conductors into:
- faces in contact with dielectric_2
- faces in contact with dielectric_1
and create different conductor description files for each.
In your list file, you will merge the different parts of the conductors using the '+' keyword at the end of the 'C' lines.
You will also need an additional file describing the pure dielectric interfaces, i.e. the interfaces between dielectric_1 and dielectric_2. This will be your 'D' line statement (tip: watch out the in/out dielectric reference point definition, otherwise you swap dielectric_1 with dielectric_2 and get inconsistent results)
You can find some examples in the 'samples' directory of FasterCap.
Best Regards,
Enrico
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omar
8 Posts |
Posted - May 04 2017 : 22:42:04
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should the list file be like this ?
* conductorA to dielectric_1 interface
C conductor_1.txt 0.0000000025 0.0 0.0 0.0 +
* conductorA to dielectric_2 interface
C conductor_2.txt 0.000000005 0.0 0.0 0.0
* conductorB to dielectric_1 interface
C conductor_1.txt 0.0000000025 0.0 140 0.0 +
* conductorB to dielectric_2 interface
C conductor_2.txt 0.000000005 0.0 140 0.0
* conductorC to dielectric_1 interface
C conductor_1.txt 0.0000000025 0.0 280 0.0 +
* conductorC to dielectric_2 interface
C conductor_2.txt 0.000000005 0.0 280 0.0
* conductorD to dielectric_1 interface
C conductor_1.txt 0.0000000025 0.0 420 0.0 +
* conductorD to dielectric_2 interface
C conductor_2.txt 0.000000005 0.0 420 0.0
* dielectric_2 to dielectric_1 interface
D dielectric.txt 0.0000000025 0.000000005 0.0 70 0.0 0.0 0.0 0.0 - 0xff0000ff
D dielectric.txt 0.0000000025 0.000000005 0.0 210 0.0 0.0 0.0 0.0 - 0xff0000ff
D dielectric.txt 0.0000000025 0.000000005 0.0 350 0.0 0.0 0.0 0.0 - 0xff0000ff
Omar Alaa |
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omar
8 Posts |
Posted - May 05 2017 : 13:57:01
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When I try the above code, FasterCap keeps crashing and giving error "overlapping panels"...how can I fix this ?
Omar Alaa |
Edited by - omar on May 05 2017 16:10:44 |
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Enrico
545 Posts |
Posted - May 05 2017 : 23:53:35
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Your input list file is probably not ok. You may have left the same panel definitions in multiple files, this is the 'overlapping panel' issue.
Also, I notice that in your list file you are re-using three times the same conductor_1.txt and conductor_2.txt files. However if you structure is a sandwich, the first conductor on the top will have 7 sides in contact with dielectric_1, and only one side (the bottom) in contact with dielectric_2; while the central conductor will have the top and bottom sides in contact with dielectric_2, and another case for the thir conductor (top in contact with dielectric_2, other sides with dielectric_1). So I'm afraid you need to split the panels composing the conductors in three different ways. Note that the same panel definitions cannot be repeated: no panel is allowed to overlap, as you already noticed.
Best Regards,
Enrico
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omar
8 Posts |
Posted - May 06 2017 : 08:51:17
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I managed to solve the overlap between panel at the same plane (by splitting the files), however I still get "overlapping panels" if a panel touches just one edge of another panel (one horizontal and another vertical) since in my design conductors and dielectric are touching each other so the horizontal panel of conductor is touching vertical panel of dielectric. In such case, I think I can't solve the error by splitting.So should I separate such panels with a very small distance ? or there's something I'm missing ?
Omar Alaa |
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Enrico
545 Posts |
Posted - May 07 2017 : 00:37:38
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No, this should be ok. You might have a numerical tolerance issue, please try to use permittivity with no scaling factor, and see if the 'overlapping panels' error disappears (you can always scale the results, if needed).
Otherwise, please copy&paste here the offending input files (all files), and I'll check them; in alternative, you can send them to me via email.
Best Regards,
Enrico
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omar
8 Posts |
Posted - May 07 2017 : 15:31:20
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I removed the dielectric scaling and now I have degenerate quadrilateral panels and non-negative off-diagonal warnings.
You can get the files using the link below as I failed to send them to your email
ht*ps://drive.google.com/open?id=0BynLHDHXMIFCdHN4YzZ2Qkxkb1k
Thank you so much
Omar Alaa |
Edited by - omar on May 07 2017 15:32:01 |
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Enrico
545 Posts |
Posted - May 09 2017 : 11:52:31
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I'm afraid you have wrong quadrilateral definitions.
Let's take for instance the last two lines of the file "Aggressor1_interface_dielectric1.txt":
Q 1 0.0 0.0 0.0 0.0 0.0 140 0.0 70 0.0 0.0 70 140
Q 1 5000 0.0 0.0 5000 0.0 140 5000 70 0.0 5000 70 140
You can see that these should be quadrilaterals, but some of the corners are wrong. They should read:
Q 1 0.0 0.0 0.0 0.0 0.0 140 0.0 70 140 0.0 70 0.0
Q 1 5000 0.0 0.0 5000 0.0 140 5000 70 140 5000 70 0.0
The same is true for the other files.
However, I also see you are trying to use high permittivity ratios (3.5 vs. 50). This is actually a numerical issue, not preventing the convergence of the solution, but possibly leading to wrong results, depending on the aggressor vs. victim conductors. This is not a software code issue, but a fundamental numerical limitation of the method used. For more details you can refer to Tausch, Johannes and Jacob White, "Capacitance extraction of 3-D conductor systems in dielectric media with high-permittivity ratios." IEEE transactions on microwave theory and techniques 47.1 (1999): 18-26. You can find the article freely available online (just look it up on scholar.google.com)
Best Regards,
Enrico
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omar
8 Posts |
Posted - May 09 2017 : 13:19:35
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Thank you so much!
One last question, how to understand the output matrix ? This matrix represents coupling between 5 wires, so for example if I want to know the coupling cap. between wires "g3_2" and "g1_1", will it be the intersection between row 3 & column 1...or row 1 & column 3 ?
Dimension 5 x 5
g1_1 1.23633e-005 -1.0083e-005 -6.14429e-007 -1.70333e-007 -7.31482e-007
g2_2 -9.93744e-006 2.05033e-005 -9.58907e-006 -6.75631e-007 -3.31844e-008
g3_2 -6.89219e-007 -9.32184e-006 2.0563e-005 -9.68364e-006 -6.26639e-007
g4_2 -9.06731e-008 -7.39387e-007 -9.32406e-006 2.04214e-005 -9.96292e-006
g5_3 -7.84637e-007 -9.99456e-008 -6.83277e-007 -9.76881e-006 1.23056e-005
Omar Alaa |
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Enrico
545 Posts |
Posted - May 09 2017 : 15:51:44
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Please refer to our white paper "The Maxwell Capacitance Matrix".
You can find it under the 'literature' tab in our web pages.
Best Regards,
Enrico
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modeling integrated circuit interconnect coupling
