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 Trouble with 'not diagonally dominant' warning
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brodym

USA
19 Posts

Posted - May 30 2019 :  11:29:54  Show Profile  Reply with Quote
I have been struggling eliminating the following errors when running both Fast and FasterCap.

Warning: capacitance matrix is not diagonally dominant due to row 1
Warning: capacitance matrix is not diagonally dominant due to row 4

Scaling the structure to a larger size and improving discretizations in the dielectric surfaces seemed to fix many issues, but I cannot get rid of the following two warnings. The example files have a lower number of discretizations than what I normally run, but the result is the same.

Certainly I need to clean up some of the dielectric surfaces a bit, and I am considering improving the discretizations on the conductors. However before I invested too much more time, I figured I would ask here first. Maybe I missing something very fundamental.

Here is a link to a temporary repo I set up to see my files:ht ps://brodym@bitbucket.org/brodym/temp-files.git

Thank you,

Brody

Brody Mahoney

brodym

USA
19 Posts

Posted - May 30 2019 :  11:32:22  Show Profile  Reply with Quote
The hyperlink got formatted oddly above. Here it is in plain text:
ht*ps://brodym@bitbucket.org/brodym/temp-files.git


Brody Mahoney
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Enrico

399 Posts

Posted - May 30 2019 :  18:11:12  Show Profile  Reply with Quote
Dear Brody,

don't worry about the link being re-formatted, this is an anti-spam measure. We want to keep the forum open w/o email address verification, but in doing so, we get spammers - and we need to avoid they can use direct external links, so the hyperlinks get blurred, but you can still use them 'manually', that's the idea.

Related to your problem, the matrix I get is :

g1_RingFWD  1.50161e-008 -1.50917e-008 -2.54098e-009 -7.93436e-010 
g2_RingREV  -1.26199e-008 2.41973e-008 -6.44466e-009 -1.50535e-009 
g3_RingFWD  -1.54766e-009 -6.46556e-009 2.42207e-008 -1.257e-008 
g4_RingREV  -7.29904e-010 -2.51741e-009 -1.51154e-008 1.49643e-008


and of course you can observe it is not diagonal dominant. Actually the issue is that you have high level of couplings, so the off-diagonal contributions are almost the same as the values on the diagonal. Coupled with numerical tolerances, this causes the warning. You may also notice that this matrix I got from a first simulation is not perfectly symmetrical. Here you may want to enforce symmetry (actually FastCap does that inside the code, FasterCap instead exposes the direct result) and actually it is the right way to share the error in the off-diagonal components. But you may play a bit more with the parameters to get a more symmetrical result as well - for instance, using a Galerkin scheme already improves the symmetry and lowers a bit the amount of non-diagonal dominance.
Remark: I've not checked in detail your input geometry, the above are general comments. Asymmetry may also come from issues in the definition of the dielectric interfaces, in particular if you have overlapping panels (conductors with dielectrics, or dielectric with dielectric).

Best Regards,
Enrico



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brodym

USA
19 Posts

Posted - May 30 2019 :  21:47:13  Show Profile  Reply with Quote
Thank you Enrico,

I will try your recommendations. I also realized that I may have some tiny overlap regions affecting row 1 and row 4.

Will let you know as soon as I get it tested.

Brody Mahoney
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brodym

USA
19 Posts

Posted - May 31 2019 :  08:00:14  Show Profile  Reply with Quote
Enrico,

Thanks again for your help. Unfortunately all the modifications I made didn't help or make non-negative off diagonal elements more likely. The good news is that I can get what seem like very accurate numbers for my application, without warnings, when I remove the dielectric layers. So for the moment there is no emergency to fix the warnings. With just the conductors FasterCap gives warning-free matrices by the second iteration on each run. So I suspect the dielectric layers are the culprit.

I would like to figure out what is causing the warnings and how to rectify it for future models.

Thank you,

Brody Mahoney
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Enrico

399 Posts

Posted - Jun 03 2019 :  15:22:28  Show Profile  Reply with Quote
Today I had some more time and analyzed your input files in more detail.

There are more than one issue, however the main one is that you dielectric interface directly cuts in half the conductors. E.g. the dielectric interface:

D fastcap_TopFace_D.qui 1.0 3.0 0.0 0.0 2.6098500000000004e-05 0.0 0.0 5.219700000000001e-05 -

is halfway between these the top and bottom of the Layer 0 spiral:

C fastcap_bot_FWD.qui 1.0 0.0 0.0 0.0 +
C fastcap_out_FWD.qui 1.0 0.0 0.0 0.0 +
C fastcap_in_FWD.qui 1.0 0.0 0.0 0.0 +
C fastcap_top_FWD.qui 3.0 0.0 0.0 0.0

You should not be doing that. It is not enough that the panels on the bottom are specified in contact with relative permittivity = 1 and the ones on the top with relative permittivity = 3. In fact, the sides are cut through! You should interrupt the dielectric interface in correspondence of the spiral, and divide the sides in two.

As a next as good approximation, since your spiral is wide but thin, you can neglect the sides (and the starter/ender panels). Let's comment them out (using only Layer 0 and Layer 1) and you will see that your matrix becomes immediately diagonally dominant, as expected.

* Layer 0
C fastcap_bot_FWD.qui 1.0 0.0 0.0 0.0 +
*C fastcap_out_FWD.qui 1.0 0.0 0.0 0.0 +
*C fastcap_in_FWD.qui 1.0 0.0 0.0 0.0 +
C fastcap_top_FWD.qui 3.0 0.0 0.0 0.0 
*C fastcap_starter_FWD.qui 1.0 0.0 0.0 0.0 +
*C fastcap_ender_FWD.qui 1.0 0.0 0.0 0.0


* Layer 1
D fastcap_D_CONFIL.qui 1.0 3.0 0.0 0.0 0.354457 0.0 0.0 0.354457 -
D fastcap_TopFace_D.qui 1.0 3.0 0.0 0.0 2.6098500000000004e-05 0.0 0.0 5.219700000000001e-05 -  
D fastcap_D_ODD.qui 1.0 3.0 0.0 0.0 0.1772285 0.0 0.0 0.354457 -
C fastcap_top_FWD.qui 3.0 0.0 0.0 0.354457 +
*C fastcap_out_FWD.qui 3.0 0.0 0.0 0.354457 +
C fastcap_bot_FWD.qui 3.0 0.0 0.0 0.354457 +
*C fastcap_in_FWD.qui 3.0 0.0 0.0 0.354457 +
*C fastcap_starter_REV.qui 3.0 0.0 0.0 0.354457 +
*C fastcap_ender_REV.qui 3.0 0.0 0.0 0.354457


If you un-comment the previous statements, you can easily verify that you fall again in the previous issue (note that I removed one '+' statement on the 5th line, as a consequence of commenting out some lines, otherwise the conductors will be shorted together).

Note that I fixed also another issue, as all your statements as the one

D fastcap_D_ODD.qui 1.0 3.0 0.0 0.0 0.1772285 0.0 0.0 0.354457 -

Actually missed a space

D fastcap_D_ODD.qui 1.0 3.0 0.0 0.0 0.17722850.0 0.0 0.354457 -

Last point is about the definition of the reference point position. While your definition still works, I recommend against going down to very small offsets w.r.t. the panel positions (in your case you are in the order of 1e-5), as this might create numerical issues. You are better off defining a reference point position at least away 1/10 from the plane relative to the plane dimensions. It does not matter if the reference point happens to be inside a different region, as it is evaluated only in respect to the dielectric interface it refers to.

Hope to have cleaned out your issue!

Best Regards,
Enrico

BTW if you are able to script Python, I would advise to use FreeCAD for generating the geometries, as you can easily perform booleans on solids and surfaces, and then triangulate the result. It makes it easier to build complex geometries (the full EM workbench will come to that, for the time being we made some scrpts available that help exporting to FasterCap format).

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