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 FasterCap and FastCap2
 Modeling printed circuit board
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Pietrow

5 Posts

Posted - Dec 04 2018 :  12:23:42  Show Profile  Reply with Quote
Hello,

I try to use FastCap2 and FasterCap to model the parasitic capacitance of a printed circuit board (PCB).

Perhaps it's useful to explain in some detail (apologies if this is obvious).

It is a two-layer board, and I do not model the solder mask that comes on top of the copper. The geometry is therefore the board substrate (1.5 mm thick, about 30 mm by 30 mm, relative permittivity 4), with copper traces on the top and the bottom. The copper is thin (35 um) and sees air on one side and the board one the other. Both the top and bottom copper consist of multiple nets.

If I model the copper only (ignoring the substrate) I get very reasonable results both with FastCap2 and FasterCap.

I have however problems with the N statement in FastCap2. I tried the form that works in FasterCap:
N g1_GND GND
as well as
N GND%GROUP1 GND

but both give a "bad line format" error. Is the N statement supported in FastCap2?

I then tried to add the substrate.

Based on the original FastCap manual my initial idea was to use B elements, but it seems neither FastCap2 nor FasterCap supports them (is this correct?).

Could you please tell me the best way to proceed? In the 2015 forum topic
"How can I set dielectric boundary?" (ht*ps://w*w.fastfieldsolvers.com/forum/topic.asp?TOPIC_ID=1103) it was noted two parallel conductors could be used (one in contact with the board, one in contact with the air).

However, at the same time it was noted that this would give numerical problems. The geometry is about 30 mm long, and the copper is 35 um thick; will FasterCap handle these two parallel conductor correctly?

Thanks in advance for any advice.

Enrico

399 Posts

Posted - Dec 06 2018 :  12:53:25  Show Profile  Reply with Quote
Dear Pietro,

you are right, the B element has never been implemented.

However, from what I understand from your description, you should not strictly need it. Your traces will have a thickness, so you should model them as 3D objects, not as flat lines. In this case, the bottom of the trace will be in contact with the PCB, therefore you specify there the PCB permittivity. while the top and the sides of the trace will be in contact with air (if you neglect the solder resist), therefore you specify here the air permittivity instead.

Be also aware that you need to cut the PCB-air interface where there is metal, otherwise the boundary constraints are specified twice. This actually simple means that no panel, either C or D, can overlap with any other panel.

Hope this helps,
Enrico
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Pietrow

5 Posts

Posted - Dec 07 2018 :  10:12:12  Show Profile  Reply with Quote
Hello Enrico,

Many thanks for your answers.

I had implemented the solution you suggest, but I ran into severe numerical problems. I assume this is not unexpected with such an aspect ratio? The copper thickness is 35 um; although I have reduced the board size, it is still 20 x 15 mm.

I did not implement the side walls of the copper, thinking that this would not matter. I try to add these and see if that changes anything.

If my script is correct, there is no overlap between C and D panels, but it is difficult to check visually. Maybe I should try to check it programmatically after meshing, but it seems a rather difficult problem.

Regards, Pietro.
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Pietrow

5 Posts

Posted - Dec 07 2018 :  14:27:39  Show Profile  Reply with Quote
Minor update, I implemented adding the side walls and it does not help convergence.
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Enrico

399 Posts

Posted - Dec 11 2018 :  00:26:13  Show Profile  Reply with Quote
Dear Pietro,

one element that may hinder convergence is high geometrical ratios in the panels, or in the elements of the panels; i.e. long and thin triangles, or the co-existence of 'big' triangles together with 'small' triangles. This might call for additional refinement, and most probably also requires lowering the '-d' parameter (as explained in the samples about parallel plate capacitors).

To trouble-clear your structure, I can suggest you to reduce it to the minimum offending input; that usually helps sorting out what the issue is. Expect anyway slower convergence when you have dielectric interfaces.

Best Regards,
Enrico
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Pietrow

5 Posts

Posted - Dec 17 2018 :  07:20:47  Show Profile  Reply with Quote
Hello Enrico,

Thanks for all your help.

I can't find the text for the parallel-plate example, sorry, but I did find your interesting explanation in ht*ps://w*w.fastfieldsolvers.com/forum/topic.asp?TOPIC_ID=952 which helps.

I tried with -d and indeed, that decreases the simulation time. I do not fully understand the effect of this parameter, is there a detailed explanation somewhere? Would it be correct to assume decreasing the interaction coefficient essentially causes the solver to accept a less refined mesh and therefore a less converged solution?

The matrix that results with -d 0.15 is still somewhat suspect (not symmetric):

Dimension 3 x 3
GND 1.26737e-012 -3.4109e-013 -4.41965e-013
NET1 -2.7948e-013 3.93851e-013 -4.01231e-014
NET2 -3.79475e-013 -3.94966e-014 5.01619e-013

Above 0.15 the convergence is still exceedingly slow.

Regards, Pietro.
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Enrico

399 Posts

Posted - Dec 18 2018 :  18:55:56  Show Profile  Reply with Quote
Dear Pietro,

the file I was talking about is called 'capacitor_simple.lst' and is located in the 'Samples' directory, please see the online embedded help from FasterCap for the location of the directory on your system.

I C&P here the file for your reference:

* Simple parallel plate capacitor
* 
*
* This capacitor is made by two square metal contacts
* embedded in an homogeneous dielectric medium
*
* If fringing fields are neglected, the capacitance as per analytical formula
* is e0*er*S/d where S is the surface of the armors and d is their distance.
* In this case S = 1, d = 0.01, er = 1, therefore C = 8.854e-12 * 1 * 1 / 0.001 = 8.854e-9
*
* Remark: given the high geometrical ratio 1:1000 between the plate side and
* the plate distance, for proper solution convergence you need to set FasterCap's
* '-d' parameter to 0.1 or lower values.
*
* 

* lower contact
C plate.txt  1.0  0.0 0.0 0.0

* upper contact
C plate.txt  1.0  0.0 0.0 0.001


But I must say that your interpretation

quote:
Would it be correct to assume decreasing the interaction coefficient essentially causes the solver to accept a less refined mesh and therefore a less converged solution?


is not correct. The -d parameter should not be used to trade off a less refined solution. The parameter is important when there are high geometrical ratios in your simulation model, as in this case the solver engine requires more links between panels, i.e. cannot approximate too much even for medium-spaced panels. From the embedded online FasterCap help again:


quote:
'Direct potential interaction coefficient to mesh refinement ratio (-d)' controls the degree of matrix compression. FasterCap stores the panels set and their relationships ('links') in a hierarchical structure, representing the interaction matrix. The '-d' parameter specifies the compression of the links with respect to the panels mesh information as specified with the 'Mesh relative refinement value (-m)' parameter (either manually set or automatically calculated in the 'Auto' mode). A lower value of the '-d' parameter means more links per panel on the average, and in principle a more accurate result; but simulation time will increase accordingly.



Hope this helps.
Enrico


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Pietrow

5 Posts

Posted - Dec 20 2018 :  09:48:05  Show Profile  Reply with Quote
Hello Enrico,

Ok, that is clearer now. I thought I had read the documentation reasonably well but it seems I missed a lot :/.

I'll let it run over the weekend and use the result as the final capacitance. Thanks again for all your help.

Merry Christmas and a happy new year.

Best regards, Pietro.

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