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allen
USA
3 Posts |
 Posted - Apr 30 2015 : 18:44:25
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Hi,
I'm new to this forum and have a question:
I have traces running on PCB inner layer sandwiched by FR4 material and solder resist on top and bottom. How can I describe these FR4 and SR layers? Can I use kind of plane to define the layers surface and assign different Dk on two side, like below:
* traces in middle
C trace.txt 3.4 0.0 0.0 0.0
* top air
D separation.txt 3.4 1 0.0 0.0 0.2 0.1 0.1 0.3 -
* top solder resist
D separation.txt 3.4 3.4 0.0 0.0 0.1 0.1 0.1 0.2 -
* FR4
* traces in middle
C trace.txt 3.4 0.0 0.0 0.0
* FR4
D separation.txt 3.4 3.4 0.0 0.0 -0.1 0.1 0.1 -0.2 -
* bottom solder resist
D separation.txt 3.4 1 0.0 0.0 -0.2 0.1 0.1 -0.3 -
* bottom air
Many thanks!
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Enrico
545 Posts |
Posted - May 04 2015 : 22:51:21
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Sure you can, this is what 'D' elements are made for.
However two notes of caution, as these are the most commonly made errors:
1) you must NOT overlap any panel, I mean ANY panel: dielectric and conductor as well. Dielectric panels are representing an interface between two different dielectrics (one of which can be, of course, air), NOT an interface between a conductor and a dielectric
2) for the reason above, if your conductor is in contact with different materials with different permittivity, you must split your conductor in multiple parts (i.e. multiple 'C' statements) each of which specifies a different permittivity (corresponding of course to the dielectric medium it is in contact with) and electrically connected with the '+' character at the end of every line, like:
C trace_top.txt 1.0 0.0 0.0 0.0 +
C trace_bottom.txt 3.4 0.0 0.0 0.0
Best Regards,
Enrico |
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allen
USA
3 Posts |
Posted - May 06 2015 : 01:18:01
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Enrico:
Thank you for your answer!
1). I knew that conductor and dielectric can't be overlapped. What I need is, that I define top and bottom dielectric panels, and define only conductive traces running between top and bottom panels. It like traces soaking in the FR4 material. I only define the top and bottom surface of FR4.
2). So, if the trace running on top of FR4, I have to split trace into two parts, bottom with FR4 permittivity and top+side with solder resist permittivity. Can I raise the trace to have very small gap between FR4 and have whole trace sitting in solder resist permittivity? Will this cause some error in simulation result?
WHat will be happened if I mass up the inperm and outperm values like below:
Top dielectric panel have perm=1 on top and perm=3.4 on bottom (defined by reference);
bottom dielectric panel have perm=1 on both top and bottom.
Regards!
allen
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Enrico
545 Posts |
Posted - May 07 2015 : 11:46:29
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quote:
1). I knew that conductor and dielectric can't be overlapped. What I need is, that I define top and bottom dielectric panels, and define only conductive traces running between top and bottom panels. It like traces soaking in the FR4 material. I only define the top and bottom surface of FR4.
Ok this can be done
quote:
2). So, if the trace running on top of FR4, I have to split trace into two parts, bottom with FR4 permittivity and top+side with solder resist permittivity. Can I raise the trace to have very small gap between FR4 and have whole trace sitting in solder resist permittivity? Will this cause some error in simulation result?
Yes you can do that, but very small gaps between conductors and dielectrics (as well as between conductors, or dielectrics) introduce numerical difficulties, as the potential matrix becomes more and more badly conditioned. While FasterCap can handle these situations, there will be an unneeded increase in the number of panels, links and gmres iterations. So I would strongly recommend to split the conductor, and define instead small gaps only when really needed.
quote:
WHat will be happened if I mass up the inperm and outperm values like below:
Top dielectric panel have perm=1 on top and perm=3.4 on bottom (defined by reference);
bottom dielectric panel have perm=1 on both top and bottom.
I'm not sure I got your question. Yes you can have different permittivities for different dielectric interfaces (different 'D' declarations). You can even define a dummy dielectric interface (i.e. with same permittivity on both sides) but this would be dummy, and will be ignored by FasterCap.
Best Regards,
Enrico
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allen
USA
3 Posts |
Posted - May 20 2015 : 23:28:21
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Enrico:
Thank you for your answer and I'm doing some exercise to compare the results.
Thank you again!
at |
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How can I set dielectric boundary?
