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Arya
USA
4 Posts |
 Posted - Mar 19 2015 : 22:30:16
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Hi,
I'm trying to make a simple Interdigitated Capacitor over a dielectric place in FastCap2 (Here is a link to show you the basic structure:
imgur.com/VVMQ4vd
).
I modified the cube.txt file that comes with the download to make it longer and more rectangle like to act as the fingers for the capacitor, and simply put them together by making the distance between them zero in the .lst file. I thought that by doing this, the software would recognize the capacitor as just two interleaved structures, and give me the cap values but instead it sees each cube as a separate component and it gives me a big matrix showing the capacitance between each cube, even though there is no distance between some of the cubes and they should be simulated as one structure.
Also, the simulation never converges/stops with a low allowable error, so I have to increase the allowable error to get it to converge/stop.
Is there a better way of connecting the fingers than making the distance between them zero? Any help/comment is appreciated. Below is all the code I am using:
*************This is the .lst file that puts the structure together*****
*the 3 finger section
C finger.txt 2.0 -1.0 -2.0 0.0 0xffffff
C finger.txt 2.0 -1.0 0.25 0.0 0xffffff
C finger.txt 2.0 -1.0 2.5 0.0 0xffffff
C finger_long.txt 2.0 -1.5 -2.0 0.0 0xffffff
*the 2 finger section
C finger.txt 2.0 -0.5 1.375 0.0 0xffffff
C finger.txt 2.0 -0.5 -0.875 0.0 0xffffff
C finger_long.txt 2.0 3.5 -2.0 0.0 0xffffff
D gndplane_10x10.txt 1.0 5.0 -5.0 -5.0 0.0 0.0 0.0 1.0 0xffff00ff
********* This is the finger.txt file **************
* front left
Q mycube 4.0 0.5 0.0 4.0 0.0 0.0 4.0 0.0 0.5 4.0 0.5 0.5
* front right
Q mycube 0.0 0.5 0.0 4.0 0.5 0.0 4.0 0.5 0.5 0.0 0.5 0.5
* back left
Q mycube 4.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.5 4.0 0.0 0.5
* back right
Q mycube 0.0 0.0 0.0 0.0 0.5 0.0 0.0 0.5 0.5 0.0 0.0 0.5
* bottom
Q mycube 0.0 0.0 0.0 4.0 0.0 0.0 4.0 0.5 0.0 0.0 0.5 0.0
* top
Q mycube 0.0 0.0 0.5 4.0 0.0 0.5 4.0 0.5 0.5 0.0 0.5 0.5
****************This is the finger_long.txt file******************
* front left
Q mycube 0.5 5.0 0.0 0.5 0.0 0.0 0.5 0.0 0.5 0.5 5.0 0.5
* front right
Q mycube 0.0 5.0 0.0 0.5 5.0 0.0 0.5 5.0 0.5 0.0 5.0 0.5
* back left
Q mycube 0.5 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.5 0.5 0.0 0.5
* back right
Q mycube 0.0 0.0 0.0 0.0 5.0 0.0 0.0 5.0 0.5 0.0 0.0 0.5
* bottom
Q mycube 0.0 0.0 0.0 0.5 0.0 0.0 0.5 5.0 0.0 0.0 5.0 0.0
* top
Q mycube 0.0 0.0 0.5 0.5 0.0 0.5 0.5 5.0 0.5 0.0 5.0 0.5
Thanks,
Arya |
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Enrico
548 Posts |
Posted - Mar 20 2015 : 10:55:53
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FastCap2 is not able to recognize conductors as connected together only because geometrically they touch. Actually, recognize touching solids or surfaces is an entire branch of 3D research.
You must tell FastCap2 / FasterCap explicitly that conductors are connected together (even if not touching!). This is done with the '+' character at the end of the 'C' statement.
Watch out however that if you made conductors touch, you will have overlapping panels. This is on the other hand forbidden, and you will have problems in converging, as the potential matrix will be badly conditioned, as it represents a non-physical situation.
By the way, you can find a valid example of interdigitated capacitor in the FasterCap samples.
Best Regards,
Enrico
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Arya
USA
4 Posts |
Posted - Mar 20 2015 : 22:19:37
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quote:
Originally posted by Enrico
Watch out however that if you made conductors touch, you will have overlapping panels.
Thank you very much for your response Enrico. I understand what I was doing wrong. I made 2 separate "finger" files, one called fingerx2 and fingerx3, and each one has the appropriate panel commented out in it, so when I connect them to my finger_long file with + signs, they do not have a panel in the side that they are connected to finger_long. This way there would not be any overlapping panels.
I can run the file with the "Stop when relative error is lower than (-a)" field in FasterCap set to 0.1 and I do get a 2x2 cap matrix (as expected), but when I lower the error limit to 0.01, it does not converge.
Do you have any suggestions on how I can fix this and run at lower error limits?
Here are my updated files:
************* The .lst file ***********************
*the 3 finger section
C fingerx3.txt 2.0 -1.0 -2.0 0.0 +
C fingerx3.txt 2.0 -1.0 0.25 0.0 +
C fingerx3.txt 2.0 -1.0 2.5 0.0 +
C finger_long.txt 2.0 -1.5 -2.0 0.0 0xffffff
*the 2 finger section
C fingerx2.txt 2.0 -0.5 1.375 0.0 +
C fingerx2.txt 2.0 -0.5 -0.875 0.0 +
C finger_long.txt 2.0 3.5 -2.0 0.0 0xffffff
D gndplane_10x10.txt 1.0 5.0 -5.0 -5.0 0.0 0.0 0.0 1.0 0xff12c3
******************** The fingerx2 file **********************
* front left
*Q mycube 4.0 0.5 0.0 4.0 0.0 0.0 4.0 0.0 0.5 4.0 0.5 0.5
* front right
Q mycube 0.0 0.5 0.0 4.0 0.5 0.0 4.0 0.5 0.5 0.0 0.5 0.5
* back left
Q mycube 4.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.5 4.0 0.0 0.5
* back right
Q mycube 0.0 0.0 0.0 0.0 0.5 0.0 0.0 0.5 0.5 0.0 0.0 0.5
* bottom
Q mycube 0.0 0.0 0.0 4.0 0.0 0.0 4.0 0.5 0.0 0.0 0.5 0.0
* top
Q mycube 0.0 0.0 0.5 4.0 0.0 0.5 4.0 0.5 0.5 0.0 0.5 0.5
**************** The fingerx3 file**********************
* front left
Q mycube 4.0 0.5 0.0 4.0 0.0 0.0 4.0 0.0 0.5 4.0 0.5 0.5
* front right
Q mycube 0.0 0.5 0.0 4.0 0.5 0.0 4.0 0.5 0.5 0.0 0.5 0.5
* back left
Q mycube 4.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.5 4.0 0.0 0.5
* back right
*Q mycube 0.0 0.0 0.0 0.0 0.5 0.0 0.0 0.5 0.5 0.0 0.0 0.5
* bottom
Q mycube 0.0 0.0 0.0 4.0 0.0 0.0 4.0 0.5 0.0 0.0 0.5 0.0
* top
Q mycube 0.0 0.0 0.5 4.0 0.0 0.5 4.0 0.5 0.5 0.0 0.5 0.5
Thanks,
Arya |
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Enrico
548 Posts |
Posted - Mar 23 2015 : 18:17:18
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You still have the same issue: no panel can overlap, either conductor panels, or dielectric panels. Your dielectric plane is overlapping with the panels on the bottom of the interdigitated capacitor plates.
You should cut the dielectric where the conductors are. However, this is not enough. Actually, you need to specify a different permittivity for the conductor panels 'in contact' with the dielectric medium below the capacitor with respect to the one for the conductor panels 'in contact' with the air.
In a nutshell, you need to split each intedigitated capacitor plate in two geometry files, one for the top&sides and one for the bottom. Then in the list file you need to specify dielectric constant = 1.0 for the top&sides, and 5.0 for the bottom. You then merge the two in a single conductor with the '+' character at the end of the 'C' statement definitions.
As a reference, you can look at the FasterCap sample file interdigitated_capacitor_with_diel.lst:
* Interdigitated capacitor with dielectric
*
*
* Run in FasterCap lowering the -d parameter to 0.3, due to the high coupling of
* the two combs
*
C combltop.txt 1.0 0.0 0.0 0.0 +
C comblbot.txt 3.0 0.0 0.0 0.0
C combrtop.txt 1.0 0.0 0.0 0.0 +
C combrbot.txt 3.0 0.0 0.0 0.0
C gndplane.txt 3.0 0.0 0.0 0.0 +
C gndplanebot.txt 1.0 0.0 0.0 0.0
* reference point here is dummy, since each panel in the definition
* file 'dielshell.txt' contains its own reference point
D dielshell.txt 1.0 3.0 0.0 0.0 0.0 0.0 0.0 0.0
Best Regards,
Enrico
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Arya
USA
4 Posts |
Posted - Mar 23 2015 : 18:59:03
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quote:
Originally posted by Enrico
D dielshell.txt
That was actually one of my questions: The very first file I looked into was the interdigitated_capacitor_with_diel.lst. But from what I understand all the files called in interdigitated_capacitor_with_diel.lst are mesh files based on triangles (they start with T), and it looks like some program was used to generate them. Is there a specific program within Fast Field Solvers that I can use to generate the mesh for shapes I want? I looked into the help files and I couldn't find anything; all I found in my installation directory were some executables which I believe make some pre-defined shapes.
Also, you mentioned cutting the dielectric plane, which I was able to see in the interdigitated_capacitor_with_diel.lst file, but I'm really not sure how to do that (make those cuts). I guess to summarize, my main question is how can I generate the mesh files for different shapes with fast field solvers?
Thanks,
Arya |
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Enrico
548 Posts |
Posted - Mar 24 2015 : 18:06:27
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I have already touched this topic in other threads, the latest one is 'Overlapping panels in FasterCap' (in the FasterCap forum as well).
Please check that thread and let me know if you need further help.
Best Regards,
Enrico
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Arya
USA
4 Posts |
Posted - Mar 25 2015 : 19:05:36
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So, I reviewed some of the other posts in the forums, and from what I can gather, I should use FreeCad to generate the mesh files and import them into fastfieldsolver, is that correct?
Is the exported FreeCad mesh file compatible with fastfieldsolver/fastercap, Or do I need to modify it somehow?
Thanks,
Arya |
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Enrico
548 Posts |
Posted - Mar 27 2015 : 12:04:27
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No, the key is that FreeCAD (besides being free) is fully scriptable. So the Python macro shown in the post I referred to is exporting the geometry directly in FasterCap format.
You need some manual work to create the list file, putting together the different conductors / part of conductors, but the hard task of modelling complex shapes or cuts is dealt with by FreeCAD.
Best Regards,
Enrico |
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Interdigitated Capacitor
