|T O P I C R E V I E W
||Posted - Jan 13 2023 : 16:19:15
I have recently created a new repository on github, ht*ps://github.com/RTimothyEdwards/capiche/, which is supposed to thoroughly analyze a complete CMOS process metal stack using FasterCap in 2D mode. The SkyWater sky130 process stackup is provided as an example, and I am trying to validate the FasterCap results against capacitance tables from SkyWater.
For the most part, it works well and gives meaningful results. However, for two-wire problems for which there is a 2x2 matrix, I am often getting a solution with unequal off-diagonal elements. I have checked over my input files and I don't see anything obviously wrong with them. I have tried various FasterCap options, but the solution always converges on the same numbers, and always with unequal off-diagonal elements.
I took the approach of averaging the two values. However, I have a case where I am analyzing the effect of the amount of fringe capacitance coupling from the sidewall of a metal wire down to a wire underneath. I have two simulations: The first is a wire over a conducting plane. The second is a wire over another wire which is at the position of the conducting plane in the first simulation. The difference between the two simulations is that the first simulation has a scalar solution (wire to conducting plane) and the second simulation has a 2x2 matrix (wire to 2nd wire, with a substrate underneath). The substrate in the 2nd simulation is more or less completely shielded by the 2nd wire, so I expect both simulations to give approximately the same answer, where the 1st simulation's answer will be the single scalar output value, and the 2nd simulation's answer will be the negative of the off-diagonal elements. What I find is that one of the off-diagonal elements is pretty close to the expected result, and the other one is pretty far off. So averaging the two results also gives a value that is pretty far off of the expected result. I would like to figure out if there is something I can do to the input or to the simulation options that would fix the disagreement between the off-diagonals.
Please let me know if you need examples. I can include the input files for both of the examples cited above.
R. Timothy Edwards
|2 L A T E S T R E P L I E S (Newest First)
||Posted - Jan 16 2023 : 15:49:49
Thanks; and yes, it was good to meet you at FSiC 2022, too!
Yes, there are dielectrics in the stackup. Many, many dielectrics. And in some cases I'm not sure how to describe them properly, especially the sidewall dielectrics that are grown off the sides of wires. Undoubtedly the dielectrics are the source of the issues, since otherwise the input file is a very simple 2D arrangement of at most two wires and a conductor plane. But I would greatly appreciate it if you can look over my input file and see how I can improve it.
I will contact you by email as requested, with the example input files.
R. Timothy Edwards
||Posted - Jan 16 2023 : 12:02:59
happy to hear from you since we met in 2019 in France at the FSiC!
I watched your presentation in the 2022 FSiC and I understand the background of your question.
Yes please send me the input files, there may be different reasons; best if you send them as attachments to my email address (see the Contacts page).
One reason is also related to the dielectric interfaces, are there any?