T O P I C R E V I E W |
Graeme |
Posted - Jan 13 2019 : 11:42:02 How should I specify a conductor with different dielectrics an each side? |
7 L A T E S T R E P L I E S (Newest First) |
billa |
Posted - Oct 10 2019 : 22:41:58 Yes, i figured it out! that was exactly the case. :)quote: Originally posted by Enrico
Dear Saurabh,
probably in your case the conductors specified in the files you are trying to join with '+' have different names.
The '+' will only join conductors having the same name. In the Graeme example this worked by definition as we were reusing the same file 'plate.txt' so of course the names contained there are the same.
Hope this helps, Enrico
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Enrico |
Posted - Oct 08 2019 : 19:15:19 Dear Saurabh,
probably in your case the conductors specified in the files you are trying to join with '+' have different names.
The '+' will only join conductors having the same name. In the Graeme example this worked by definition as we were reusing the same file 'plate.txt' so of course the names contained there are the same.
Hope this helps, Enrico
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billa |
Posted - Oct 06 2019 : 16:32:15 I just dont understand why even though i have used the plus sigh, both the objects are not treated as one conductor!quote: Originally posted by billa
Dear Enrico, when i try the below given example of parallel plate capacitor it works fine.But i tried this trick with a model I am working with. However it is not treated as one conductor. I get a 3x3 matrix as an output. I am basically trying to model a horizontal conductor supported on an flat insulator. And this assembly is embedded completely in another dielectric.. can you perhaps suggest something that i can do differently? by the way there are very high geometric ratios involved in the model and i also set the "-d" parameter to be 0.07quote: Originally posted by Enrico
Dear Graeme,
this is actually possibly if your conductor has a thickness. In this case, you can refer to the example "capacitor.lst" that you can find in the FasterCap sample directory (see the online embedded help for FasterCap for the location of this directory). I report the list file here for your convenience, see the directory for the referenced geometry description files if you need them.
* Capacitor
*
* This capacitor is made by a dielectric material with relative permittivity
* equal to 3.0, sandwiched between two square metal contacts
* with finite thickness
* lower contact
C capacitor_contact_sides.txt 1.0 0.0 0.0 0.0 +
C plate.txt 1.0 0.0 0.0 0.0 +
C plate.txt 3.0 0.0 0.0 0.2
* dielectric medium
D capacitor_diel_sides.txt 1.0 3.0 0.0 0.0 0.2 0.5 0.5 0.5 - 0xa793b4ff
* upper contact
C capacitor_contact_sides.txt 1.0 0.0 0.0 0.8 +
C plate.txt 3.0 0.0 0.0 0.8 +
C plate.txt 1.0 0.0 0.0 1.0
So you actually divide your conductor in set of panels, according to the dielectric they are in contact with; and then merge them together in a single conductor using the trailing '+'.
If instead you would like to specify a zero-thickness conductor at the interface between two different permittivity mediums, I'm sorry but this is not supported at present. Most of the time, however, for realistic models you actually have a 3D thickness, so this is not a limit.
If you believe on the other hand that this is a must have feature for you, we are open for discussing a possible extension to FasterCap to support this boundary condition as well. In this case kindly contact me again via email, and I'll be happy to discuss the details with you.
Best Regards, Enrico
saurabh
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billa |
Posted - Oct 05 2019 : 19:39:29 Dear Enrico, when i try the below given example of parallel plate capacitor it works fine.But i tried this trick with a model I am working with. However it is not treated as one conductor. I get a 3x3 matrix as an output. I am basically trying to model a horizontal conductor supported on an flat insulator. And this assembly is embedded completely in another dielectric.. can you perhaps suggest something that i can do differently? by the way there are very high geometric ratios involved in the model and i also set the "-d" parameter to be 0.07quote: Originally posted by Enrico
Dear Graeme,
this is actually possibly if your conductor has a thickness. In this case, you can refer to the example "capacitor.lst" that you can find in the FasterCap sample directory (see the online embedded help for FasterCap for the location of this directory). I report the list file here for your convenience, see the directory for the referenced geometry description files if you need them.
* Capacitor
*
* This capacitor is made by a dielectric material with relative permittivity
* equal to 3.0, sandwiched between two square metal contacts
* with finite thickness
* lower contact
C capacitor_contact_sides.txt 1.0 0.0 0.0 0.0 +
C plate.txt 1.0 0.0 0.0 0.0 +
C plate.txt 3.0 0.0 0.0 0.2
* dielectric medium
D capacitor_diel_sides.txt 1.0 3.0 0.0 0.0 0.2 0.5 0.5 0.5 - 0xa793b4ff
* upper contact
C capacitor_contact_sides.txt 1.0 0.0 0.0 0.8 +
C plate.txt 3.0 0.0 0.0 0.8 +
C plate.txt 1.0 0.0 0.0 1.0
So you actually divide your conductor in set of panels, according to the dielectric they are in contact with; and then merge them together in a single conductor using the trailing '+'.
If instead you would like to specify a zero-thickness conductor at the interface between two different permittivity mediums, I'm sorry but this is not supported at present. Most of the time, however, for realistic models you actually have a 3D thickness, so this is not a limit.
If you believe on the other hand that this is a must have feature for you, we are open for discussing a possible extension to FasterCap to support this boundary condition as well. In this case kindly contact me again via email, and I'll be happy to discuss the details with you.
Best Regards, Enrico
saurabh |
Enrico |
Posted - Jan 26 2019 : 19:18:45 They specify the color when the file is visualized in FastModel (see the FastModel embedded online help). They are simply ignored by FastCap / FasterCap.
Best Regards, Enrico
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Graeme |
Posted - Jan 24 2019 : 23:46:51 Thank you. I'll try it.
What are the hex numbers after the + and - signs in the lst file?
* lower contact C capacitor_contact_sides.txt 1.0 0.0 0.0 0.0 + 0xd8d8d8ff *C plate.txt 1.0 0.0 0.0 0.0 + 0xd8d8d8ff *C plate.txt 3.0 0.0 0.0 0.2 0xd8d8d8ff
* dielectric medium D capacitor_diel_sides.txt 1.0 3.0 0.0 0.0 0.2 0.5 0.5 0.5 - 0xa793b4ff
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Enrico |
Posted - Jan 15 2019 : 19:03:46 Dear Graeme,
this is actually possibly if your conductor has a thickness. In this case, you can refer to the example "capacitor.lst" that you can find in the FasterCap sample directory (see the online embedded help for FasterCap for the location of this directory). I report the list file here for your convenience, see the directory for the referenced geometry description files if you need them.
* Capacitor
*
* This capacitor is made by a dielectric material with relative permittivity
* equal to 3.0, sandwiched between two square metal contacts
* with finite thickness
* lower contact
C capacitor_contact_sides.txt 1.0 0.0 0.0 0.0 +
C plate.txt 1.0 0.0 0.0 0.0 +
C plate.txt 3.0 0.0 0.0 0.2
* dielectric medium
D capacitor_diel_sides.txt 1.0 3.0 0.0 0.0 0.2 0.5 0.5 0.5 - 0xa793b4ff
* upper contact
C capacitor_contact_sides.txt 1.0 0.0 0.0 0.8 +
C plate.txt 3.0 0.0 0.0 0.8 +
C plate.txt 1.0 0.0 0.0 1.0
So you actually divide your conductor in set of panels, according to the dielectric they are in contact with; and then merge them together in a single conductor using the trailing '+'.
If instead you would like to specify a zero-thickness conductor at the interface between two different permittivity mediums, I'm sorry but this is not supported at present. Most of the time, however, for realistic models you actually have a 3D thickness, so this is not a limit.
If you believe on the other hand that this is a must have feature for you, we are open for discussing a possible extension to FasterCap to support this boundary condition as well. In this case kindly contact me again via email, and I'll be happy to discuss the details with you.
Best Regards, Enrico
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