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FastFieldSolvers

Literature
Literature

The following sections contain different literature materials. First you can find the FastFieldSolvers white papers; then a selection from the impressive number of studies done with the aid of these solvers; and a list of the main papers using FastCap and FastHenry as golden references.

Overall, thousand of papers cite FastCap, FastHenry and FastFieldSolvers. You can search for them for instance on Google Scholar following the links 'FastCap', 'FastHenry' or 'FastFieldSolvers'.

White Papers
White Papers

The Treatment of Dielectrics in FasterCap

 

Abstract - FasterCap and FastCap2 are quasistatic capacitance solvers able to handle arbitrarily shaped conductors embedded in multiple, piecewise-constant, dielectric regions. This paper reviews the underlying theory in FasterCap's treatment of dielectric regions.

 

The Maxwell Capacitance Matrix

 

Abstract - The meaning of the Maxwell capacitance matrix is reviewed, highlighting the rationale of this matrix form in relation to the internal mechanisms of a capacitance field solver. Some practical examples also show how to use the Maxwell capacitance matrix to build a SPICE netlist.

 

ElectroMagnetic Solvers Basics

 

Abstract - The presentation summarizes some electromagnetic concepts useful to understand the basics under the hood of quasistatic ElectroMagnetic solvers and the related circuit theory. After reviewing the relations between the Maxwell equations and the circuit parameters (inductance, capacitance and resistance), the presentation deals with the concept of partial inductance and briefly discusses some high frequency effects taking place in the conductors.

 

Applications
Applications

EMC

O. Valorge, B. Gosselin, L-F. Tanguay, M. Sawan,"Electromagnetic Compatibility Modeling in Low-Noise Medical Sensor Interfaces", IEEE International Symposium on Circuits and Systems, ISCAS, 2007

 

B.J. Pierquet, T.C. Neugebauer, D.J. Perreault,"Inductance Compensation of Multiple Capacitors With Application to Common- and Differential-Mode Filters", IEEE Transactions on Power Electronics, Vol. 21, No. 6, Nov 2006

 

D. Cotter, M. Paakkinen,"Scalable PEEC-SPICE Modelling for EMI Analysis of Power Electronic Packages and Subsystems", 8th Electronics Packaging Technology Conference, EPTC, 2006

 

IC Design

D.K. Shaeffer, T.H. Lee,"A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier", IEEE Journal of Solid-State Circuits, Vol. 32, No. 5, May 1997

 

M. Tormanen, H. Sjoland,"A 25-GHz Differential LC-VCO in 90-nm CMOS", IEEE Asia Pacific Conference on Circuits and Systems, APCCAS, 2008

 

B. De Muer, C. De Ranter, J. Crols, M. Steyaert,"A Simulator-Optimizer for the Design of Very Low Phase Noise CMOS LC-Oscillators", Proceedings of ICECS '99, The 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

 

R. Thuringer,"Characterization of Integrated Lumped Inductors and Transformers", R. Thuringer Thesis, Technischen Universitaet Wien, 2002

 

A. Nainani, S. Palit, P.K. Singh, U. Ganguly, N. Krishna, J. Vasi, S. Mahapatra,"Development of A 3D Simulator for Metal Nanocrystal (NC) Flash Memories under NAND Operation", IEEE International Electron Devices Meeting, IEDM, 2007

 

Y. Wang,"Millimeter Wave Transceiver Fronted Circuits in Advanced SiGe Technology with Considerations for On-Chip Passive Component Design and Simulation", Y. Wang PhD Thesis, Cornell University, 2006

 

J. Wood, T.C. Edwards, S. Lipa,"Rotary Traveling-Wave Oscillator Arrays: A New Clock Technology", IEEE Journal of Solid-State Circuits, Vol. 36, No. 11, Nov 2001

 

T. Makkonen, S. Kondratiev, V.P. Plessky, T. Thorvaldsson, J. Koskela, J. V. Knuuttila, M.M. Salomaa,"Surface Acousting Wave Impedance Element ISM Duplexer: Modeling and Optical Analysis", IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 48, No. 3, May 2001

 

IC Packaging

E. Di Lorenzo,"Caratterizzazione Elettromagnetica di Packages Ultraminiaturizzati Applicati a Memorie Flash-EEPROM", E. Di Lorenzo Thesis, Politecnico di Milano, 1998

 

T. Arnborg, T. Johansson,"3D Characterization of RF Power Transistors", Proceedings of the 1999 International Conference on Microelectronic Test Structures, ICMTS, 1999

 

X. Qi, C.P. Yue, T. Arnborg, H.T. Soh, H. Sakai, Z. Yu, R.W. Dutton,"A Fast 3-D Modeling Approach to Electrical Parameters Extraction of Bonding Wires for RF Circuits", IEEE Transactions on Advanced Packaging, Vol. 23, No. 3, Aug 2000

 

Inductor design

V. Blaschke, J. Victory,"Accurate Inductance De-embedding Technique for Scalable Inductor Models", IEEE International Conference on Microelectronic Test Structures, Mar 2007

 

S.I. Babic, C. Akyel,"Calculating Mutual Inductance Between Circular Coils With Inclined Axes in Air", IEEE Transactions On Magnetics, Vol.44, No.7, Jul 2008

 

D. Kehrer, W. Simbuerger, H-D. Wohlmuth, A.L. Scholtz,"Modeling of Monolithic Lumped Planar Transformers up to 20 GHz", IEEE Custom Integrated Circuits Conference, 2001

 

C. Akyel, S.I. Babic, M.-M. Mahmoudi,"Mutual Inductance Calculation for Non-Coaxial Circular Air Coils with Parallel Axes", Progress in Electromagnetics Research, PIER 91, pp.287-301, 2009

 

T.N. Baig,"New Directions in the Design of MRI Gradient Coils", T.N. Baig PhD Thesis, Case Western Reserve University, 2007

 

Interconnections

A. Morabito,"Caratterizzazione e Ottimizzazione di Strutture Conduttive per Piastre a Circuito Stampato Dedicate al Trasporto di Segnali ad Alta Frequenza", A. Morabito Thesis, Università di Catania, 2003

 

A. Bansal, B. C. Paul, K. Roy,"An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 12, Dec 2006

 

A. Roy, J. Xu, M. H. Chowdhury,"Analysis of the impacts of signal slew and skew on the behavior of coupled RLC interconnects for different switching patterns", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol.18, No.2, Feb 2010

 

X-C. Li, J-F. Mao, H-F. Huang, Y. Liu,"Global Interconnect Width and Spacing Optimization for Latency, Bandwidth and Power Dissipation", IEEE Transactions On Electron Devices, Vol. 52, No. 10, Oct 2005

 

S-W. Tu, W-Z. Shen, Y-W. Chang, T-C. Chen, J-Y. Jou,"Inductance Modeling for On-Chip Interconnects", Journal of Analog Integrated Circuits and Signal Processing, Vol. 35, Issue 1, 01/04/2003

 

Y. Massoud, S. Majors, J. Kawa, T. Bustami, D. MacMillen, J. White,"Managing On-Chip Inductive Effects", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol.10, No.6, Dec 2002

 

J. Zhang, E.G. Friedman,"Mutual Inductance Modeling for Multiple RLC Interconnects with Application to Shield Insertion", Proceedings of IEEE International SOC Conference, pp. 344-347, Sep 2004

 

M. Kariyanakatte,"Optimization of Interconnect Structures", ESE526, Dec 2001

 

Z. Zhu, J. Phillips, Z-C. Ye,"Parasitic Effects Analysis of Circuit Structures", Patent US 7,853,910 B1, Dec 2010

 

S-W. Tu, J-Y. Jou, Y-W. Chang,"RLC Coupling-Aware Simulation for On-Chip Buses and their Encoding for Delay Reductions", IEEE International Symposium on Circuits and Systems, ISCAS, 2005

 

X2Y® Attenuators,"X2Y® Capacitors in IC Back-Side Mounting Applications", X2R Applicaton Note, 2006

 

E. Laermans, J.D. Geest, D.D. Zutter, F. Olyslager, S. Sercu, D. Morlion,"Modelling Differential Via Holes", IEEE Transactions on Advanced Packaging, Aug 2001

 

Magnetics

W.X. Qiang,"Theory and Modelling of Spin-Dependent Tunnelling", W.X. Qiang Master thesis, National University of Singapore, 2003

 

MEMS

L. W. Zhong,"Model Order Reduction Techniques in Microelectromechanics", L. W. Zhong PhD Thesis, National University of Singapore, 2004

 

V.M. Lubecke, B. Barber, E. Chan, D. Lopez, M.E. Gross, P. Gammel,"Self-Assembling MEMS Variable and Fixed RF Inductors", IEEE Transactions on Microwave Theory and Techniques, Vol. 49, No. 11, Nov 2001

 

Nanotechnology

A.T. Bollinger, A. Rogachev, A. Bezryadin,"Dichotomy in short superconducting nanowires: Thermal phase slippage vs. Coulomb blockade", Europhysics Letters, 76 (3), pp. 505-511, 2006

 

N. Srivastava, K. Banerjee,"Performance Analysis of Carbon Nanotube Interconnects for VLSI Applications", IEEE/ACM International Conference on Computer-Aided Design, ICCAD, 2005

 

X. Wang, Y. Ouyang, X. Li, H. Wang, J. Guo, H. Dai,"Room Temperature All Semiconducting sub-10nm Graphene Nanoribbon Field-Effect Transistors", APS Physical Review Letters, Vol. 100, Issue 20, 2008

 

Quantum Computing

R. Kalra,"Design and Modeling of Silicon Spin Qubits for Quantum Computing", Taste Of Research Summer Scholarship 2009-10, University of New South Wales, 2010

 

J. Han, P. Jonker,"Novel Computing Architecture on Arrays of Josephson Persistent Current Bits", Nanotech 2002 Vol. 1, Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems, Chapter 12: Circuit Simulation, 2002

 

K. Y. Tan, K. W. Chan, M. Mottonen, A. Morello, C. Yang, J. van Donkelaar, A. Alves, J.-M. Pirkkalainen, D. N. Jamieson, R. G. Clark, A. S. Dzurak,"Transport Spectroscopy of Single Phosphorus Donors in a Silicon Nanoscale Transistor", ACS Nano Letters, 10 (1), pp. 11–15, Feb 2010

 

RF

R.R.A. Syms, L. Solymar,"Bends in magneto-inductive waveguides", Metamaterials, Volume 4, Issue 4, pp. 161-169, Elsevier B.V., Dec 2010

 

Wireless Links

S. Atluri, M. Ghovanloo,"A Wideband Power-Efficient Inductive Wireless Link for Implantable Microelectronic Devices Using Multiple Carriers", IEEE Transactions on Circuits and Systems, Oct 2007

 

S. Atluri,"A Wideband Power-Efficient Inductive Wireless Link for Implantable Microelectronic Devices Using Multiple Carriers", Master Thesis, North Carolina State University, 2006

 

R.R. Harrison,"Designing Efficient Inductive Power Links for Implantable Devices", IEEE International Symposium on Circuits and Systems, ISCAS, 2007

 

C. Reinhold, P. Scholz, W. John, U. Hilleringmann,"Efficient Antenna Design of Inductive Coupled RFID-Systems with High Power Demand", Journal of Communications, Vol. 2, No. 6, Nov 2007

 

B. Waters,"High Q Resonant Coupling and RF-DC Conversion for Wireless Power Transfer", Columbia University, Dec 2009

 

K.M. Silay, C. Dehollain, M. Declercq,"Improvement of Power Efficiency of Inductive Links for Implantable Devices", Research in Microelectronics and Electronics, PRIME, 2008

 

R. Puers, K.V. Schuylenbergh, M. Catrysse, B. Hermans,"Wireless Inductive Transfer of Power and Data", Analog Circuit Design, pp. 395–414, 2006

 

Citations as Golden References
Citations as Golden References

Wei Zhuang,"A 3-D Capacitance Extraction Algorithm based on Kernel Independent Hierarchical Method and Geometric Moments", Master Thesis, Texas A&M University, May 2006

 

W. Chai, D. Jiao, C-K. Koh,"A Direct Integral-Equation Solver of Linear Complexity for Large-Scale 3D Capacitance and Impedance Extraction", ACM/IEEE 46th Design Automation Conference, DAC '09, 2009

 

Fangquing Yu, Weiping Shi,"A Divide-and-Conquer Algorithm for 3D Capacitance Extraction", Proceedings of ISQED, pp.253~258, 2004

 

Weiping Shi, Jianguo Liu, Naveen Kakani, Tiejun Yu,"A Fast Hierarchical Algorithm for Three-Dimensional Capacitance Extraction", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 3, Mar 2002

 

S. Kapur, D. Long,"IES3: A Fast Integral Equation Solver for Efficient 3-Dimensional Extraction", IEEE/ACM International Conference on Computer-Aided Design, 1997

 

S. Kapur, J. Zhao,"A Fast Method of Moments Solver for efficient parameter extraction of MCMs", Proceedings of the 34th annual conference on Design automation conference (DAC '97), 1997

 

Y. C. Pan, L. X. Wan, W.C. Chew,"A Fast Multipone Method Based Calculation of the Capacitance Matrix in a Stratified Medium", IEEE Antennas and Propagation Society International Symposium, 2000

 

D. Gope, S. Chakraborty, V. Jandhyala,"A Fast Parasitic Extractor Based on Low-Rand Multilevel Matrix Compression for Conductor and Dielectric Modeling in Microelectronics and MEMS", Design Automation Conference, 41st Conference on (DAC'04), 2004

 

S. A. Teo, B. L. Ooi, S. T. Chew, M. S. Leong,"A Fast PEEC Technique for Full-Wave Parameters Extraction of Distributed Elements", IEEE Microwave and Wireless Components Letters, Vol. 11, No. 5, May 2001

 

Z. Zhu, W. Hong,"A Generalized Algorithm for the Capacitance Extraction of 3-D VLSI Interconnects", IEEE Transactions on Microwave Theory and Techniques, Vol. 47, No. 10, Oct 1999

 

W. Hong, W-K. Sun, Z-H Zhu, H. Ji, B. Song, W. W-M. Dai,"A Novel Dimension-Reduction Technique for the Capacitance Extraction of 3-D VLSI Interconnects", IEEE Transactions on Microwave Theory and Techniques, Vol. 46, No. 8, Aug 1998

 

Y. Yi, P. Li, V. Sarin, W. Shi,"A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 11, Nov 2008

 

H. Mahawar, V. Sarin, W. Shi,"A Solenoidal Basis Method For Efficient Inductance Extraction", In Proceedings of DAC'2002, pp.751~756, 2002

 

Z. Yang, Z. Wang, S. Fang,"A Virtual 3-D Multipole Accelerated Extractor for VLSI Parasitic Interconnect Capacitance", Proceedings of the 2001 Asia and South Pacific Design Automation Conference, 2001

 

Ong Eng Teo,"Accurate and Efficient Three-Dimensional Electrostatics Analysis using Singular Boundary Elements and Fast Fourier Transform on Multipoles (FFTM)", PhD Thesis, National University of Singapore, 2003

 

N.P. van der Meijs, T. Smedes,"Accurate Interconnect Modeling: Towards Multi-million Transistor Chips As Microwave Circuits", Technical Digest of the 1996 IEEE/ACM Int. Conf. on Computer-Aided Design,, pp.244~251, 1996

 

W. Yu, Z. Wang,"An Efficient Quasi-Multiple Medium Algorithm for the Capacitance Extraction of Actual 3-D VLSI Interconnects", In Proceedings of ASP-DAC'2001. pp.366~372, 2001

 

W. Ding, G. Wang,"An Efficient Preconditioning Scheme for Fast Hierarchical Method in 3-D Capacitance Extraction of IC interconnect", 7th International Conference on ASIC, Guilin, Guangxi, China, Oct 2007

 

M. Bächtold, J. G. Korvink, H. Baltes,"An Error Indicator and Automatic Adaptive Meshing for 3D Electrostatic Boundary Element Simulations", Boundary Elements XIX, Transaction: Modelling and Simulation volume 19, 1997

 

M. Bächtold, M. Emmenegger, J. G. Korvink, H. Baltes,"An Error Indicator and Automatic Adaptive Meshing for Electrostatic Boundary Element Simulations", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 12, Dec 1997

 

H. Kim, C. C-P. Chen,"Be Careful of Self and Mutual Inductance Formulae", N/A, N/A

 

U. Geigenmueller, N.P. van der Meijs,"Cartesian Multipole Based Numerical Integration for 3D Capacitance Extraction", European Design and Test Conference. ED&TC 97. Proceedings, 1997

 

S. Gupta, L. T. Pileggi,"CHIME: Coupled Hierarchical Inductance Model Evaluation", DAC '04 Proceedings of the 41st annual Design Automation Conference, 2004

 

A. Heldring, J.M. Rius, J.M. Tamayo, J. Parrón,"Compressed Block-Decomposition Algorithm for Fast Capacitance Extraction", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 2, 2008

 

Y. Nakashima, M. Ikeda, K. Asada,"Computational Cost Reduction in Extracting Inductance", ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design, 2001

 

Y. Yi, S. Yan, V. Sarin, W. Shi,"Development of Fast 3D Parasitic Extraction using Hierarchical Method for Integrated Circuits and Packages", Antennas and Propagation Society International Symposium, 2008

 

D. Gope, I. Chowdhury, V. Jandhyala,"DiMES: Multilevel Fast Direct Solver based on Multipole Expansions for Parasitic Extraction of Massively Coupled 3D Microelectronic Structures", Design Automation Conference, Proceedings. 42nd, 2005

 

C.F. Wang, L.W. Li, P.S. Kooi, M.S. Leong,"Efficient Capacitance Computation for 3D Structures Based on AIM", Antennas and Propagation Society International Symposium. IEEE, 2000

 

N. Soveiko, M. S. Nakhla,"Efficient Capacitance Extraction Computations in Wavelet Domain", IEEE Transactions on Circuits and Systems - I: Fundamental Theory and Applications, Vol. 47, No. 5, May 2000

 

Z. Ye, W. Yu, Z. Yu,"Efficient 3-D Capacitance Extraction Considering Lossy Substrate With Multilayered Green’s Function", IEEE Transactions on Microwave Theory and Techniques, Vol. 54, No. 5, May 2006

 

W. Yu, M. Zhang, Z. Wang,"Efficient 3-D Extraction of Interconnect Capacitance Considering Floating Metal Fills With Boundary Element Method", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 1, Jan 2006

 

W. Wang, J. Fang, Y. Chen,"Efficient and Accurate Extraction of Frequency-Dependent Resistance and Inductance Parameters of Interconnects", Electrical Performance of Electronic Packaging, 1999

 

S. Yan,"Efficient Numerical Methods for Capacitance Extraction based on Boundary Element Method", PhD Thesis, Texas A&M University, Dec 2005

 

M. W. Beattie, L. T. Pileggi,"Electromagnetic Parasitic Extraction via a Multipole Method with Hierarchical Refinement", ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, 1999

 

W. Yu, Z. Wang, X. Hong,"Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics", ICCD'03 Proceedings of the 21st International Conference on Computer Design, 2003

 

W. Yu, Z. Wang,"Enhanced QMM-BEM Solver for Three-Dimensional Multiple-Dielectric Capacitance Extraction Within the Finite Domain", IEEE Transactions on Microwave Theory and Techniques, Vol. 52, No. 2, Feb 2004

 

M. Beattie, B. Krauter, L. Alatan, L. Pileggi,"Equipotential Shells for Efficient Inductance Extraction", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 1, Jan 2001

 

G. Zhong, C-K. Koh,"Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects", Proceedings of 2002 IEEE International Conference on Computer Design, 2002

 

H. H. Pham, A. Nathan,"Exponential Expansion for Field Computation and Capacitance Extraction", IEEE Transactions on Circuits and Systems - I: Fundamental Theory and Applications, Vol. 48, No. 10, Oct 2001

 

J. Wang, J. White,"Fast Algorithms for Computing Electrostatic Geometric Sensitivities", International Conference on Simulation of Semiconductor Processes and Devices, SISPAD '97, 1997

 

C.F. Wang, L.W. Li, P.S. Kooi, M.S. Leong,"Fast Capacitance Computation Using Three-Dimensional Second-Kind Integral Equation and AIM", IEEE Antennas and Propagation Society International Symposium, 2001

 

S. Yan, V. Sarin, W. Shi,"Fast Capacitance Extraction Using Inexact Factorization", IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging, 2004

 

H. Xuefei,"Fast Fourier Transform on Multipoles Algorithm for Elasticity and Stokes Flow", PhD Thesis, National University of Singapore, 2007

 

P. J. Restle, A. E. Ruehli, S.G. Walker, G. Papadopoulos,"Full-Wave PEEC Time-Domain Method for the Modeling of On-Chip Interconnects", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 7, Jul 2001

 

T. Lu, Z. Wang, W. Yu,"Hierarchical Block Boundary-Element Method (HBBEM): A Fast Field Solver for 3-D Capacitance Extraction", IEEE Transactions on Microwave Theory and Techniques, Vol. 52, No. 1, Jan 2004

 

A. J. Van Genderen, N. P. van der Meijs,"Hierarchical Extraction of 3D Interconnect Capacitances in Large Regular VLSI Structures", ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, 1993

 

S. Kapur, D. E. Long,"High-Order Nystrom Schemes for Efficient 3-D Capacitance Extraction", IEEE International Conference on Computer-Aided Design, ICCAD 98. Digest of Technical Papers, IEEE/ACM, 1998

 

A. Devgan, H. Ji, W. Dai,"How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K", IEEE/ACM International Conference on Computer Aided Design, ICCAD-2000, 2000

 

R. Jiang, Y-H. Chang, C. C-P. Chen,"ICCAP: A Linear Time Sparse Transformation and Reordering Algorithm for 3D BEM Capacitance Extraction", In Proceedings of DAC'2005, pp.163~166, 2005

 

Y. Yi, P. Li, V. Sarin, W. Shi,"Impedance Extraction for 3-D Structures with Multiple Dielectrics using Preconditioned Boundary Element Method", IEEE/ACM International Conference on Computer-Aided Design, 2007. ICCAD, 2007

 

S. Yan, J. Liu, W. Shi,"Improving Boundary Element Methods for Parasitic Extraction", Proceedings of the ASP-DAC 2003. Asia and South Pacific Design Automation Conference, 2003

 

T-H. Chen, C. Luk, C. C-P. Chen,"INDUCTWISE: Inductance-Wise Interconnect Simulator and Extractor", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 7, Jul 2003

 

H. Ji, A. Devgan, W. Dai,"Ksim: A Stable and Efficient RKC Simulator for Capturing On-Chip Inductance Effect", Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference, 2001

 

S. Kapur, D. E. Long,"Large-Scale Capacitance Calculation", Proceedings of 37th Design Automation Conference, 2000

 

S. Kapur, D. E. Long,"Large-Scale FullWave Simulation", Proceedings of the 41st annual Design Automation Conference, DAC '04, 2004

 

S. Balakrishnan, J. H. Park, H. Kim, Y-M. Lee, C. C-P. Chen,"Linear Time Hierarchical Capacitance Extraction Without Multipole Expansion", ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors, 2001

 

P.J.H. Elias, G.P.J.F.M. Maas,"Matrix Reduction in IC and PCB Parasitics Extraction Programs", Proc. ProRISC/IEEE on Circuits, Systems and Signal Processing, 1996

 

D. Gope, V. Jandhyala,"Oct-Tree-Based Multilevel Low-Rank Decomposition Algorithm for Rapid 3-D Parasitic Extraction", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 11, 01/11/2004

 

T. Lin, M. W. Beattie, L.T. Pileggi,"On the Efficacy of Simplified 2D On-Chip Inductance Models", DAC '02 Proceedings of the 39th annual Design Automation Conference, 2002

 

D. Gope, V. Jandhyala,"PILOT: A Fast Algorithm for Enhanced 3D Parasitic Extraction Efficiency", Electrical Performance of Electronic Packaging, 2003

 

D. Wen, W. Gaofeng,"Preconditioning Matrix for Fast Hierarchical Method in 3-D Capacitance Extraction of IC interconnect", International Symposium on Electromagnetic Compatibility, EMC, 2007

 

A. E. Ruehli, A.C. Cangellaris,"Progress in the Methodologies for the Electrical Modeling of Interconnects and Electronic Packages", Proceedings of the IEEE, May 2001

 

K. Zeng, J. G. Korvink,"Rapid Extraction of Capacitances and Inductances in MMICS", 2nd International Conference on Microwave and Millimeter Wave Technology, ICMMT, 2000

 

S. Yan, V. Sarin, W. Shi,"SeaPEEC: A Comprehensive Hierarchical Parasitic Extraction Tool Based on Partial Element Equivalent Circuits", N/A, N/A

 

S. Yan, V. Sarin, W. Shi,"Sparse Transformations and Preconditioners for Hierarchical 3-D Capacitance Extraction with Multiple Dielectrics", DAC '04 Proceedings of the 41st annual Design Automation Conference, 2004

 

S. Yan, V. Sarin, W. Shi,"Sparse Transformations and Preconditioners for 3-D Capacitance Extraction", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Sep 2005

 

Z. He, M. Celik, L. Pileggi,"SPIE: Sparse Partial Inductance Extraction", Proceedings of the 34th Design Automation Conference, 1997

 

S. Kim, D. P. Neikirk,"Time Domain Multiconductor Transmission Line Analysis Using Effective Internal Impedance", IEEE 6th Topical Meeting on Electrical Performance of Electronic Packaging, 1997

 

A. Pacelli,"Vector potential equivalent circuit for efficient modeling of interconnect inductance", Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2, 2003

 

H. Yu, L. He,"Vector Potential Equivalent Circuit Based on PEEC Inversion", Proceedings of Design Automation Conference, 2003

 

A.J. Dammers, N.P. van der Meijs,"Virtual Screening: A Step Towards a Sparse Partial Inductance Matrix", IEEE/ACM International Conference on Computer-Aided Design, 1999

 

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